Regularity and Symmetry as a Base for Efficient Realization of Reversible Logic Circuits

We introduce a Reversible Programmable Gate Array (RPGA) based on regular structure to realize binary functions in reversible logic. This structure, called a 2 * 2 Net Structure, allows for more efficient realization of symmetric functions than the methods shown by previous authors. In addition, it realizes many non-symmetric functions even without variable repetition. Our synthesis method to RPGAs allows to realize arbitrary symmetric function in a completely regular structure of reversible gates with smaller “garbage” than the previously presented papers. Because every Boolean function is symmetrizable by repeating input variables, our method is applicable to arbitrary multi-input, multi-output Boolean functions and realizes such arbitrary function in a circuit with a relatively small number of garbage gate outputs. The method can be also used in classical logic. Its advantages in terms of numbers of gates and inputs/outputs are especially seen for symmetric or incompletely specified functions with many outputs

Delay and Yield of CNFET-Based Circuits in the Presence of Variations

The aggressive scaling of CMOS circuits is approaching the atomic and quantum physical limits [1], and therefore extensive research is being conducted on devices made with III-V and II-VI semiconductors, and with more exotic materials like grapheme, and various nanotubes

Synthesis for regularity using decision diagrams

Presented are new algorithms for synthesizing Boolean functions as regular logic structures. These regular structures can be mapped directly (without place&route) to a standard-cell library designed for regularity or to locally-connected programmable devices. The advantage of regular structures is that for a planar embedding the number of nodes in the expansion level grows at most linearly with the number of expansion variables. Regularity offers a predicable solution to hard problems arising in layout, at no extra cost or at the cost of increasing the number of gates, but without necessarily increasing circuit area. Increasing the number of logic levels does not translate into an increase in overall circuit delay, because regular, neighbor-to-neighbor connections reduce the wire delay, the dominant factor in deep sub-micron technology. This paper proposes new techniques which lead to less variable repetition and significantly improve the performance of synthesis algorithms. Experimental results much better than previously published data are very encouraging. 1

Thermal Management in 3D IC Designs for Nano-CMOS Technologies: Analysis on Graphene- vs. Graphite-based TIM

With a high thermal conductivity of 3000-5000 W/m-K, Graphene outstands almost all materials in effective lateral heat spreading. Will introduction of 2D monolayer graphene in 3D-IC help in vertical heat conduction too? In this work, we investigate the impact of Graphene- and Graphite- -based inter-die thermal interface material (TIM) on the peak temperature of the 3D-IC. We compare configurations of additional intermediate layer (IL) of monolayer graphene, graphite and copper materials along with TIM. Simulations show a peak temperature reduction of up to 500C in GSRC benchmarks. Role of thermal conductivity and the additional IL critical thickness in peak temperature reduction is also investigated. Our discussion encompasses the vertical thermal profile impact on TSV delay and peak temperature dependence on TIM material, thermal-conductivity and thickness. Lastly, of all configurations, we suggest to further investigate a very promising cost-effective graphite-based inter-die TIM along with graphite-based heat spreaders, to compensate the poor heat dissipation problem in 3D ICs

Logic Synthesis for a Regular Layout

New algorithms for generating a regular two-dimensional layout representation for multi-output, incompletely specified Boolean functions, called, Pseudo-Symmetric Binary Decision Diagrams (PSBDDs), are presented. The regular structure of the function representation allows accurate prediction of post-layout areas and delays before the layout is physically generated. It simplifies power estimation on the gate level and allows for more accurate power optimization. The theoretical background of the new diagrams, which are based on ideas from contact networks, and the form of decision diagrams for symmetric functions is discussed. PSBDDs are especially well suited for deep sub-micron technologies where the delay of interconnections limits the device performance. Our experimental results are very good and show that symmetrization of reallife benchmark functions can be done efficiently

Multi-Level Programmable Arrays for Sub-Micron Technology Based on Symmetries

Regular layout is a fundamental concept in VLSI design which can have application in custom design for submicron technologies, designing new architectures for fine-grain Field Programmable Gate Arrays (FPGAs) and Electrically Programmable logic Devices (EPLDs), and minimization of logic functions for existing FPGAs. PLAs are well known examples of regular layouts. Lattice diagrams are another type of regular layouts that have been recently introduced for layout-driven logic synthesis. In this paper we extend and combine theses two ideas, by introducing the multi-level PLA-like structures, composed from multi-output (pseudo) symmetrical lattice planes and other planes (multi-input, multi-output regular blocks). The main idea is to decompose a non-symmetric general function to planes, in order to realize as much as possible of the function with totally symmetric and regularly connected planes

Rs3dplace: Monolithic 3D IC Placement Using Reinforcement Learning and Simulated Annealing

We propose a novel Reinforcement Learning (RL) and Simulated Annealing (SA)-based placement algorithm (RS3DPlace), which, to the best of our knowledge, is the first machine learning approach for Monolithic 3D ICs (M3D). Application of Machine Learning to physical design of 2D and 3D VLSI ICs is an emerging area. Recently proposed learning algorithms for the placement problem consider only 2D ICs and still exhibit memory issues and learning problems in large search spaces. RS3DPlace uses the learning ability of RL to quickly estimate a preliminary solution, which SA later uses to generate an improved final solution. To address memory issues, RS3DPlace uses the approximate method for state representation which reduces the memory complexity and allows more than one kind of perturbation to improve learning efficiency in large search spaces. The current implementation is for the gate-level M3D design style, but it can be extended to other M3D design styles and other 2D and 3D physical design optimization problems. To illustrate the effectiveness of RS3DPlace, we tested it for 8-128-bit MUX-based right arithmetic shifter circuits and a circuit with non-regular connections compared to Mux-based shifters, which are optimized in 2-layered M3D technology. The experimental results show that RS3DPlace solves the M3D placement of 896 variables. Experimental results also show on average 16% improvement in overall cost function in comparison to Random Initialized SA (RandSA)

Detecting Support-Reducing Bound Sets Using Two-Cofactor Symmetries

Detecting support-reducing bound sets is an important step in Boolean decomposition. It affects both the quality and the runtime of several applications in technology mapping and re-synthesis. This paper presents an efficient heuristic method for detecting support-reducing bound sets using two-cofactor symmetries. Experiments on the MCNC and ITC benchmarks show an average 40x speedup over the published exhaustive method for bound set construction